Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles

In’this paper, a new family of dynamic logic gates called Dualrail DataDriven Dynamic Logic (D4L) is introduced. In this logic family, the synchronization clock signal has been eliminated and correct precharge and evaluation sequmcing is maintained by appropriate use of data instances. The methodology and characteristics of d L are demonstrated in the design of a CLA 32-b adder and a 17-b high-speed multiplier. Based on VHDL simulations, the D4L implemented 32-b adder has 23% less switchingactivity than a comparable Domino adder and for d L multiplier switchingactivity is 14.5% less than its Domino rival. HSPICE simulation in a O.@m CMOS process shows that @L has a 17% power saving over Domino in a 32-b CLA adder design and a 10% saving in a 17 -b multiplier design while a @L adder has 8% less delay than a Domino one.